1. Field of Disclosure
The present invention relates to testing of integrated circuits and more specifically to optimal representation of connection information indicating the manner in which communication paths of peripherals can be connected to I/O pins during testing of an integrated circuit.
2. Related Art
An integrated circuit (IC) may contain several peripherals, with each peripheral representing a logic block with defined inputs and corresponding outputs. In general, design of a complex IC typically entails dividing the overall design into several logical blocks, with each logical block being referred to as a peripheral.
ICs are typically tested/validated after fabrication. Such testing generally entails providing pre-specified inputs to each peripheral and examining the output signals on specific input/output (I/O) pins. In general, each peripheral is provided communication paths, which provide a conductive path to the respective I/O pins.
It is generally desirable to minimize the number of I/O pins for reasons such as to limit the die size area, reduce cost, etc. Accordingly, a multiplexor/demux (referred to as a mux) is employed associated with each I/O pin, with the multiplexor being operable to connect a desired communication path to the I/O.
Thus, during testing of an IC, a tester generally chooses a desired set of peripherals that are required for a specific test, and causes the muxes to be programmed such that the communication paths of the set of peripherals are connected to the respective I/O pins.
As tests for different purposes are conducted sequentially, it is generally required that different sets of peripherals are used and muxes be programmed to connect different communication paths (of corresponding peripherals) to different I/O pins. Further, for enhanced speed/efficiency, it is generally desirable that such connections be effected programmatically (as opposed to manual determination of which communication path is to be connected to which I/O pin).
Integral to such programmatic configuration is representation of connection information indicating the manner in which communication paths of different peripherals can be connected to different I/O pins during testing of an integrated circuit. The representation may need to be optimal in the sense that a desired balance of various criteria such as speed and resource usage (e.g., memory requirement, processing requirements).
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.